The present invention relates generally to a process for fabricating metal-insulator-semiconductor (MIS) integrated circuits, and more particularly, to the processing step of annealing a fabricated wafer by passing a laser beam through the semiconductor wafer from the back surface thereof to the semiconductor-insulator interface to effect localized heating of the insulator at the semiconductor-insulator interface, the laser beam being of a wavelength which makes the semiconductor wafer substantially transparent and the insulator substantially absorbent to the laser beam.
In the process for fabricating metal-insulator-semiconductor integrated circuits, such as metal-oxide-semiconductors (MOS) and metal-nitride-oxide-semiconductors (MNOS), for example, much attention is paid to the semiconductor-insulator interface because the characteristics of such devices are strongly dependent on the properties of this interface. It is well known that during the fabrication process, interface states and fixed oxide charge are formed at the semiconductor-insulator interface primarily in the insulator material. The presence of the interface states have a tendency to degrade the transconductance and sub-threshold behavior of the transistors of the integrated circuit, while the fixed oxide charge is known to change the threshold voltages thereof. An annealing step is generally performed during the fabrication process to reduce the effects of the interface states and fixed oxide charge.
Capacitance-voltage (CV) curves are used to determine the density of the interface states and the amounts of fixed oxide charge present at the interface. The CV curves may be generated by applying a potential across the semiconductor-insulator interface and varying the voltage in a periodic sawtooth fashion from say -10 volts to +10 volts, for example, at a frequency commensurate with the amount of capacitance present. Curves 10 and 12 in FIG. 1A are exemplary of low frequency and high frequency CV curves, respectively, developed from a semiconductor-insulator interface. The difference between the capacitance measured between the high frequency and low frequency curves 10 and 12, respectively, at -V.sub.G min. is representative of the density of the interface states, denoted by N.sub.st. In addition, the shift of the curves 10 and 12 from the ordinate of the graph is a measure of the fixed oxide charge present at the interface, denoted by Qss. The effects of an ideal annealing step is shown by the curves 10' and 12' in FIG. 1B. In the optimum, the annealing step causes the CV curves 10' and 12' to come together at -V.sub.G min. and shifts the curves 10' and 12' closer to the ordinate of the graph which in effect illustrates a substantial reduction in both the density of the interface states and the amount of fixed oxide charge present at the interface.
Conventional furnace annealing techniques in which a fabricated wafer is disposed in a furnace at elevated temperatures for a period of time for improving the interface quality thereof has certain inherent shortcomings, as, for example, stresses caused by differential thermal expansion due to the difference in materials at the semiconductor-insulator interface. In addition, since most of the semiconductor wafers are doped silicon, heating of the silicon during the annealing step may cause undesirable changes in the dopant profile thereof. Furthermore, in most instances, the furnace annealing step is performed before the device is metallized. The subsequent metallization step required to complete the fabrication of the wafer may degrade any benefits gained from the interface annealing step.
Experimentation has been performed with other annealing techniques, such as annealing with an argon (Ar.sup.+) laser beam, for example, with promising results being reported. In the Ar.sup.+ laser annealing of MOS devices, a laser beam is passed through the insulator from the top or front surface thereof to the interface between the insulator and semiconductor materials. The Ar.sup.+ laser beam is of such a wavelength to be transmitted through the insulator layer, which may be SiO.sub.2, for example, and absorbs strongly in the underlying silicon wafer. One drawback of this annealing process is that it must be performed prior to the metallization step in the fabrication process, otherwise there will be laser beam reflections from the metal circuit paths on the front surface of the fabricated wafer. Another drawback of the Ar.sup.+ laser beam annealing is that the energy of the laser beam is absorbed strongly in the silicon which may cause undesirable heating effects in the silicon resulting in the redistribution of dopant impurities which should be avoided, if possible.
From the above, it can be appreciated that while the present and promising annealing techniques perform the function intended adequately, they do have their shortcomings. Thus, it is preferred to keep the better qualities of the aforementioned annealing techniques while eliminating most if not all of their shortcomings. The annealing method described herebelow in a preferred embodiment is felt to accomplish these goals.